This invention relates in general to complementary metal oxide semiconductor (CMOS) devices having gate electrodes and conductors constructed of polysilicon. More particularly, this invention is directed to a process for fabricating such CMOS devices such that the polysilicon gate electrodes and conductors are of a single conductivity, single impurity type.
As used herein, the following definitions apply:
"Impurity type" refers in the conventional sense to n-type (donor) or p-type (acceptor) impurities;
"Conductivity" is used in the conventional sense as being a measure of the ability to conduct current, and is the reciprocal of resistivity;
"Conductivity type", "n-type conductivity" and "p-type conductivity" refer to the dominant impurity-type, n-type or p-type, which a material contains. Thus the conductivity type of a polycrystalline silicon material which is heavily doped with n-type impurities and lightly doped with p-type impurities would be n-type conductivity, while the same material doped solely with p-type impurities would have p-type conductivity.
In the fabrication of CMOS devices, it is preferable to use silicon gate technology rather than metal gate technology. This preference for silicon gate technology arises from several advantages inherent in this type of technology. In particular, the use of silicon gate technology provides an area savings due to the better tolerances arising from the self-aligning nature of such gate structures, due to the ability to provide an additional layer of interconnect and due to the availability of buried contacts.
The earliest silicon-gate fabrication processes produced CMOS devices having polysilicon electrodes and conductors of both n-type and p-type conductivity. This dual conductivity scheme resulted from the dual impurity nature of CMOS devices. In particular, these early fabrication processes were designed to dope a gate electrode of a transistor when the transistor's source and drain regions were formed. In this way, the polysilicon gate electrodes and conductors associated with the p-channel transistors were doped with p-type impurities during formation of the source and drain regions of the p-channel transistors. Similarly, the polysilicon gate electrodes and conductors associated with the n-channel transistors were made to be n-type. Accordingly, CMOS devices fabricated in this manner had some gate electrodes and conductors which were p-type and some gate electrodes and conductors which were n-type. This dual conductivity scheme presents several design and fabrication problems. The most prominent problem associated with devices fabricated in this manner is that a p-type gate electrode and/or conductor cannot be connected directly to an n-type gate electrode and/or conductor. A metal bridge must be interposed between gate electrodes and/or conductors of different conductivity types to provide a good ohmic contact between them. Use of such a metal bridge, however, is highly undesirable because it occupies a significant amount of chip area, which can only be used for this connection function. This problem is aggravated in LSI and VLSI circuits where efficient use of chip area is of the utmost importance. Accordingly, it is highly desirable to fabricate CMOS devices to have gate electrodes and conductors of a single conductivity type to make more efficient use of chip area.
A technique for forming CMOS devices having single conductivity electrodes and conductors is known in the prior art. This technique comprises the steps of heavily doping all of the polysilicon gate electrodes and conductors with n-type impurities (such as phosphorus or arsenic) prior to formation of the source and drain regions. Thereafter, the source and drain regions of the n-type and p-type channel transistors are formed by diffusing or implanting suitable dopants into the substrate. Typically, the n-channel transistors are formed by implanting phosphorus or arsenic into the substrate while the p-channel transistors are formed by implanting boron into the substrate. The formation of the source and drain regions of the p-channel transistors introduces p-type impurities (boron) into the previously n-doped gate electrodes and conductors associated with these transistors. In implementing this technique, the initial, n-type impurity is sufficiently greater than the p-type concentration so that these electrodes and conductors remain n-type even after the p-type impurities have been introduced during the formation of the p-channel transistors. In short, the gate electrodes and conductors associated with the p-channel transistors are doped with two impurities but, because of the n-type overdoping, exhibit the same n-type conductivity as the gate electrodes and conductors associated with the n-channel transistors.
While the above mentioned processing technique achieves the desired result of producing a CMOS device with gate electrodes and conductors of a single conductivity type, the introduction of boron into the gate electrodes and conductors associated with the p-channel transistors during formation of their source and drain regions produces a potential problem when scaled small geometry (i.e. very thin gate insulator) devices are being formed. This problem arises from the propensity of boron to diffuse from the gate electrodes (associated with the p-channel transistors), through the thin oxide layer which separates the gate electrodes from the underlying substrate, and into the underlying substrate, thereby changing the threshold voltage of the p-channel transistors or producing a short between their source and drain regions. In either case, this boron penetration has a detrimental effect upon the operation of the resulting device as fully discussed by J. T. Clemens and E. F. Labuda in their publication entitled "Impurity Diffusion in SiO.sub.2 Layers and Related Effects on the MOS Properties of the Si-Gate Technology," Electrochemical Society Extended Abstracts, Vol. 74-1, Abstract No. 46, p. 125, May 1974. Accordingly, this processing technique is unsuitable for the fabrication of silicon-gate VLSI circuits and other CMOS devices having very thin gate oxide p-channel transistors.
It is therefore an object of the present invention to provide a method for forming integrated circuit devices having polysilicon gate electrodes and conductors of a single conductivity, single impurity type, wherein the gate electrodes and conductors are doped independently of the substrate regions such as source and drain regions.
Another object of the present invention is to provide a method for forming CMOS devices having single conductivity gate electrodes and conductors, which method is applicable to CMOS VLSI circuits and other CMOS devices having small geometries.
It is an added object of the present invention to provide a method for the fabrication of CMOS devices having a single layer of polysilicon suitably doped to provide areas of high conductivity for interconnect lines and areas of low conductivity for resistors.
These and other objects of the invention will be apparent from the following description.